With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies. All of these processes cause the related CMOS IC products to become more susceptible to damage due to ESD events. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits on the IC from ESD damage.
FIG. 1A illustrates a conventional ESD protection circuit 100, and FIGS. 1B and 1D illustrate a plan view and a cross-sectional view of the GGNMOS 106 illustrated in FIG. 1A. As shown in FIG. 1A, the ESD protection circuit 100 includes control circuitry 102 connected to the gate of an output driver 104 and a gate-grounded NMOS transistor (GGNMOS) 106 serving as an ESD protection device. The trigger voltage, Vt1, of the output driver 104 is usually lower than the trigger voltage of the GGNMOS protection device 106 during an ESD event due to the gate of the output driver 106 being at an unknown state during the ESD event. The ESD event may damage the circuitry coupled to the output driver 104 as the voltage across the output driver 104 will be triggered before the GGNMOS 106 is triggered due to the higher trigger voltage of the GGNMOS 106.
One prior art attempt to reduce the trigger voltage of the GGNMOS 106′ is illustrated in FIGS. 1C and 1E. As shown in FIG. 1C, the GGNMOS 106′ includes a P+ implantation region in the P-well below the drain. The inclusion of the P+ implantation region reduces the trigger voltage of the GGNMOS 106′ and provides enhanced protection from ESD events. However, the additional protection comes at an additional process cost for the P+ implantation.
U.S. Pat. No. 6,465,768 issued to Ker et al. discloses a substrate biasing circuit for providing a higher substrate voltage during ESD events, which, for a given ESD current, enables the trigger voltage of the GGNMOS to be reduced. However, the circuit disclosed in Ker is designed for an RC time constant of 2 μs or greater to provide protection against ESD events and at the same time protect against false triggers during powering up. However, the size of the resistor and capacitor to achieve an RC time constant of approximately 2 μs or more must be quite large taking up valuable area on an integrated circuit.
Accordingly, an improved ESD protection circuit having a relatively small size is desirable.